ASIC and FPGA verification engineers to ALTEN Lund

Our employees are our success!

Every individual is equally important in ALTEN’s success! We are driven by seeing people grow and develop, therefore we create opportunities to work with what you have passion for. This enables us to offer the most committed consultants on the market.

We believe in growing together!

This position involves participation in projects with cutting edge technology and in a high paced international environment.

The work includes:
- Specifying, evaluating and creating UVM testbench architectures
- for highspeed interface IPs.
- Development of UVM testbenches and test cases for the IPs.
- Verification planning, specification and documentation
- Design verification (regression + development verification)
- Usage of reference models (if needed)
- Constrained random testing
- Creation of Coverage matrix

Requirements
- Master of Science or similar
- Experience of creating UVM testbenches with TLM reference models
- Experience in using the System Verilog/UVM tools and methodology for IP verification.
- Good scripting skills using e.g. Python, TCL and/or Perl.
- Experience from wireless or high speed interface, ie. Ethernet.

And a plus with:
- Experience in system level verification.
- Knowledge about Formal verification.
- Knowledge in programming C, C++ and System C.
- Experience from agile development