ASIC verification engineer

The job involves IP design verification within digital ASIC & FPGA projects.
The work includes:
•        Development of UVM testbenches and test cases for IPs.
•        Debugging of test environment and design
•        Creation of Scoreboards
•        Refinement of assertions and coverage
•        Creation of relevant documentation

Most of the verification uses constrained random methodology but also
dedicated test-vectors and assertions are used.
A successful candidate is an experienced verification engineer with 5 or more
years of IP verification experience, at least half of the time using UVM
methodology.
Testbenches and verification is done using System Verilog/UVM.
Both written and spoken English skills are required. Personal profile should
also include a positive attitude, a desire to assist fellow engineers, structured
way of working, care with details and a natural talent in communicating with
others.
You enjoy working both independently and in a small diverse team and you
are focused on reaching result on time. As a person you must be thorough
and able to work with many different people.
The work will be carried out in a cross functional team using Agile ways of
working.

5 Competence Requirements
5.1 Qualification
•        Education level: Master of Science or similar

5.2 Required qualifications
•        Advanced user of System Verilog
•        Advanced user of UVM tools and methodology for IP verification.
•        Significant experience in assertions, scoreboards and coverage refinement
•        Excellent programming skills (SV, VHDL).
•        Good scripting skills using e.g. Python, TCL and/or Perl.
•        Knowledge about Agile ways of working.

5.2.1 Good to have
•        Experience of Ethernet or another high-speed interface.
•        Experience in system level verification.
•        Knowledge about Formal verification.
•        Knowledge in programming C, C++ and System C.