ASIC / FPGA Engineer

Verification planning

Verification specification

Verification environment (creation/adaptation/maintenance).

Test case creation & execution

Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used. A successful candidate is an experienced design & verification engineer with 5+ years experience of design & verification (verification shall be done using SystemVerilog/UVM).

Required skills and experiences:

Strong programming skills (VHDL, C).

Experienced in Hardware design/systemization.

Experience in system level verification.

Good knowledge in using the SystemVerilog/UVM tools and methodology.

Knowledge of verification methodology in general.

Knowledge about Formal verification is a plus.

Knowledge of High Level Synthesis using is a plus.

Scripting skills using e.g. Python, TCL and/or Perl is a plus.

Knowledge about Agile ways of working is a plus.

Duration: 12-24 months on site in Sweden, with a high probability for extensions.

Extent: Full-time, 40h/week. Paid overtime can be requested by the customer.

Compensation: Negotiable. We offer a competitive salary, primarily in the form of a longterm employment and according to Swedish standards; governmental pension plan, paid vacation, occupational pension plan, insurance package, language course support, sports activity contribution, iPad/laptop, mobile phone, etc. When applicable, family members will get permit to live and work in Sweden.