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Are You a passionate ASIC engineer, looking for a new and interesting project? Do You want to live and work in a stable country with a functioning welfare system?
Since early 2000 we have supported our clients on a vast number of projects, all over the world. Our consultant pool consist of Swedish and non Swedish consultants within the fields of embedded systems, telecommunication, online solutions and application development. Now we are looking for new candidates to come work with us as consultants, on-site with our customers in Sweden.
The job involves block design & design verification within digital ASIC & FPGA projects.
The work includes:
Design verification (regression + development verification)
Miscellaneous tasks in connection to the block design
Verification environment (creation/adaptation/maintenance).
Test case creation
Usage of uVC´s
Usage of reference models (if needed)
Constrained random testing
Creation of Coverage matrix
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.
A successful candidate is an experienced design & verification engineer with 5 or more years of IP module design & verification experience
Verification shall be done using System Verilog/UVM.
Both written and spoken English skills are required. Personal profile should also include a positive attitude, a desire to assist fellow engineers, structured way of working, care with details and a natural talent in communicating with others.
You enjoy working both independently and in a small diverse and you are focused on reaching result on time. As a person you must be thorough and able to work with many different people.
The work will be carried out in a cross functional team using Agile ways of working.
Excellent programming skills (VHDL, SV).
Experienced in Hardware design/systemization.
Experienced in HW design methodology.
Experience of SW design for an embedded environment.
Experienced in WCDMA, GSM and/or LTE systems.
Experience in system level verification is a plus.
Knowledge in using the System Verilog/UVM tools and methodology.
Knowledge of verification methodology in general.
Knowledge in programming C, C++ and System C.
Knowledge about Formal verification is a plus.
Knowledge of High Level Synthesis using e.g. the Calypto tool is a plus.
Good scripting skills using e.g. Python, TCL and/or Perl.
Knowledge of reference model development.
Knowledge about Agile ways of working is a plus.
Start: Summer 2016
Duration: 12-24 months on site in Sweden, with a high probability for extensions. One month resignation. No penalty for early resignation.
Extent: Full-time, 40h/week. Paid overtime can be requested by the customer.
Compensation - subcontractor (Schengen citizen): Negotiable. We will support you with housing and all needed registrations in Sweden (Migration board, tax authorities, etc). Paid transfer to Sweden including registered partner and children.
Compensation - employment (non Schengen citizen): Negotiable
Employment also includes; governmental pension plan, private pension plan, five weeks paid vacation, iPad/laptop, mobile phone with data plan subs