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You will be part of a high end technology project with the goal to develop and verify complex digital designs. The position involves taking responsibility for the specification, design and verification of high quality ASIC/FPGA applications and Systems.
We are currently looking for a number of ASIC Design and Verification Engineers for work with one of our clients.
Required competence ·
Relevant university education in engineering and/or related fields.
· Minimum 3-7 years of experience in working with ASIC & FPGA Development.
· Experience in Customers interactions and project deliverables.
· Experience in digital ASIC design from system study to tapeout.
· Experience with FPGA, Zynq UltraScale+ MPSoC.
· Front-end RTL Design expertise in VHDL / Verilog.
· Experience in ASIC synthesis using RTL Compiler or Synopsys Design Compiler.
· Experience with HDL simulation, synthesis, and timing closure.
· Experience in Logical equivalence checking Formality, Jasper or FormalPro.
· Experience in Static Timing Analysis using Synopsys Prime time.
· Experience in HVL System Verilog and verification methodology UVM, OVM & VMM.
· Test plan development, Execution, Functional and Code coverage.
· EDA Simulation tools Questasim/ NCSim / VCS.
· Post Silicon Debug and Validation.
· Programming language C, C++ and concepts of OOPs.
· Version control tools like CVS/ SVN/ Clear case/Perforce
· Scripting Languages Perl/Python/Shell/Tcl.
· Experience from verification of complex digital SoC designs with CPUs, DSPs.
· Knowledge of high-speed interfaces such as PCIe, USB, SATA, Ethernet, DDR3/4, LPDDR3/4.
· Knowledge ARM AXI protocol.
· Knowledge of other devices/standards such as SPI, IIC, SD, NAND, QSPI.
Aurenav Sweden filial av Aurenav LLC USA is the Swedish branch of a US company specializing in consultant services and business support.