Asic design engineer

ASIC design with some knowledge of verification and simulation on sub-system and/or chip level
At least 7 years of related experience
Sound expertise in VHDL/Verilog/System Verilog
Good Experience with C/C++, TLM/System c would be added advantage
Good Experience in Integration
Good Experience in Cadence/Synopsis flow
Good Experience in various buses, interfaces, processors, memories and controllers, and telecom related.
It is a plus if you have knowledge of Synthesis and Timing analysis for ASIC
Multi/Many-Core CPU Architecture knowledge

Swedium Global is looking for experienced ASIC Design Engineer for its project in Sweden. Work location will be in Sweden

Swedium Global is the growing System Engineering and Solution Company, offers services like Engineering R&D and Services to clients across the globe for onsite and offshore business model. We provide industry solutions to our customer through our dedicated development center in Bangalore (India) and Stockholm (Sweden).

http://www.swediumglobal.com