SW Developer for 5G HW Verification (223279)

Introduction

You will develop Verification SW (Ethel) that executes on several of the HW platforms on Ericsson Radio Systems (ERS) 4G/5G Linux Baseband units.

You are located in Kista and part of a small team with a high level of flexibility and innovation. The team is critical in proofing performance of future HW functions.

The verification SW operates at a low level, above the driver SW, that is intended to both emulate the logical flows over e.g. Ethernet and other transport protocols as used by the higher level platform SW and Radio Access application SW above it and also determine the HW performance potential in ways the higher level SW cannot.

The assignment more in detail

The verification SW operates at a low level, above the driver SW, that is intended to emulate the logical flows over Ethernet (to begin with) as used by the higher-level platform SW and Radio Access (RAT) application SW above it. At a later stage then IQ, IQC and ECP flows will be incorporated.

The short/medium term need is to work with the verification SW development on the two main platforms, the Central Processing Module (CPM) that is based on Intel and the ASIC Baseband Modules (BBM) that are based on Ericsson’s flex-ASIC EMCAs.

This verification SW is needed mainly to help to verify the Hardware Prepared requirements on the 5G Baseband products before HW release.

Verification SW is needed for this since the application SW does not generate enough load before design release of the HW.

Without this being done then a risk management decision at HW Design release is made more difficult because it is unknown what possible bottlenecks there may be at future high traffic loads and even if discovered using the real application SW it is then at too late a stage to make changes to the HW or even workarounds in the SW design.

Competence is required in the following areas:

C-programming (Including POSIX process handling, use of sockets)
Manipulation of makefiles for compilation (gcc compiler)
(Bash) Linux shell commands/scripting
Knowledge of SW version handling/storage in GIT

Desired:

Multi Core Architectures. Knowledge of SW design for ASIC based applications, ideally Ericsson EMCA (Ericsson Many Core Architecture). See also below for further details
Use of virtual platforms (SystemC) e.g. TLM, for early SW development
Verification script writing in Python
Java/Javascript programming experience
Verilog programming experience

Following competencies are also desired but not required:

Knowledge of the RTE/other API towards Intel’s NP/Fastpath architecture within the AXM.

Knowledge of how to code DSP SW to use the HW structure within the flex-ASIC EMCAs especially regarding the use of FENRIR in the Baseband ASIC (BBM).

Fenrir is a HW acceleration of the following functions:

Memory allocation
Resource scheduling
Queue handling
Timer Queue Pool
The Fenrir block is configured through the Ring Bus interface using tokens and by programming the embedded DSPs using assembler.

Almost all ASIC BBM processing involves Fenrir.

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