- Notera att ansökningsdagen för den här annonsen kan ha passerat. Läs annonsen noggrant innan du går vidare med din ansökan.
o Experienced System Verilog verification engineer
o Gate level simulation experience
o Scripting in Perl, Python, Bash or C-shell
o Good skills in working with UNIX and/or Linux
o Power estimation experience
o Low power RTL+UPF simulation and verification
o Experience on defining works flows and new ways of working
o Clearcase version control system experience
o UVM verification methodology
o Good experience in VHDL
o More than 12 years in the ASIC industry
Test Planning and Development of Verification Environment using UVM
MSc level in Electrical Engineering, Computer Science, or equivalent education.
Up to 5 years of relevant work experience.
Knowledge in C programming.
Deep understanding and experience in using System Verilog.
Very good understanding of VHDL.
Good scripting experience in Perl, Python and Shell script
Good working knowledge in Linux.
Good working knowledge of Git.
Good understanding of telecommunication protocols
The Role consists of tasks as below among others
Involved in developing test framework and test cases in ASIC verification are.
Create verification components using System Verilog.
Execute test cases.
Debug test cases.
Create documents like verification specification and reports.
Stellar Consultants is a IT consulting company that provides only highly competent consultants in service of our esteemed customers.
The work location would be at our client site. You might need to work from home or office from time to time. Travelling may be required to different client locations.
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