ASIC Verification

Role & Resposibilty:

• Test bench case creation

• Usage and development of uVC´s

• Usage of reference models

• Constrained random testing

• Creation of Coverage matrix: important to understand how to create needed Test Benches & verification output

• UVM methodology – use it & understand it

• Experience within minimum 1 or all type : Block verification / Top level verification / Formal verification

Qualifications needed:

• Experience in hardware verification in VHDL using OVM/UVM

• Experience in System level verification, formal verification

• Experience in using the System Verilog (SV) tools and UVM methodology

• Excellent programming skills in System Verilog

• Experience of Software design for an embedded environment

• Good programming skills in C and/or C++

• Knowledge of hardware design (VHDL/Verilog)

• Good knowledge of verification methodology in general

Required skills. Are you none - novice - intermediate - senior - expert on below:

• OVM / UVM

• System Verilog

• System level verification

• Formal verification

• Software design

• Programming skills in C and/or C++

• HW design (VHDL/Verilog)

• Ready to relocate (Yes/No)