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ROLE: ASIC/FPGA Verification Engineer
Job Description
You will be part of a high end technology project with the goal to develop and verify complex digital designs
Will be Responsible for Block/Sub-sys/Top level verification of ASIC/FPGA designs
Experience
5-10 years
Location:
Stockholm, Sweden
Required Competence
Experience in HVL System Verilog and verification methodology UVM, OVM & VMM
Test plan development, Execution, Functional and Code coverage
EDA Simulation tools Questasim/ NCSim / VCS
Post Silicon Debug and Validation
Programming language C, C++ and concepts of OOP?s
Version control tools like CVS/ SVN/ Clear case/Perforce
Scripting Languages Perl/Python/Shell/Tcl
Experience from verification of complex digital SoC designs with CPUs, DSPs, advanced filters, and high speed links
Candidates must be good team players with attention to detail, self-disciplined, able to manage their own time and workload, proactive and motivated
Excellent written and verbal communication skills in English
The work will be carried out at client offices around Stockholm.