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We are now looking for Synthesis and STA engineers to join our Digital Development Team within the Radio Products & Variants organization in Lund

Ericsson is investing heavily in the future 5G technology where leading-edge ASIC and FPGA development is key. Ericsson in Lund is significantly strengthening the capacity in the development of state-of-the-art digital ASIC and FPGA with a great number of talented engineers to meet this challenge.

Since 2014, Lund has been a competence center for radio network development: activities span from HW and SW product development to research and standardization.

We are looking for Experienced, Creative, and Innovative engineers to join our world class team. You will have a unique opportunity to work and gain competence in several areas such as synthesis, RTL-design, STA, integration, & timing/area/power closure. You will be part of a dynamic team where there will be opportunities for learning, trying out new roles and responsibilities and much more. Our organization works in accordance to the Lean and Agile principles with close team interaction.

Come and discover what makes YOU + ERICSSON a powerful combination

We welcome the opportunity to meet you!

You will have the opportunity to work with

- SoC level STA
- Timing constraints development
- Timing sign off
- Netlist generation & Synthesis
- Floorplan development
- Acting as main interface towards physical implementation team
- Continuously improve and optimize ways of working.
- Participate in daily and periodic agile meetings


- BSc or MSc level in Electrical Engineering, Computer Science, or equivalent education.
- At least 5 years of relevant work experience.
- Good understanding of VHDL or System Verilog.
- Significant experience of EDA tools for Synthesis & Timing/Area/Power closure

- Significant experience from Static Timing Analysis and timing sign off
- Knowledge in scripting languages (Python, Perl, TCL, Linux Shell scripting etc.)
- Experience from UNIX/Linux
- Communication and presentation skills in English are essential.
- Quality-consciousness.
- Travels may be needed but not required on a frequent basis.

Following experience will be a beneficial asset
- Multi/Many Core CPU Architecture Knowledge a plus
- Experience from source code repositories such as Clear Case and Git
- Experience with Synopsis Spyglass, Primetime, Design Compiler & Formality
- Knowledge about mobile communication standards is an advantage.
- Knowledge of floor planning and physical implementation is an advantage

Personal qualifications

You have a great interest in learning new things every day and want to make a difference. You have a very positive attitude and thrive on new challenges. You are keen to solve problems and do so creatively. Where there is change you see opportunities. You are a strong team player and a very communicative person but you also work well independently. You make sure to reach results with high quality and on time.

Ericsson provides equal employment opportunities (EEO) to all employees and applicants for employment without regard to race, color, religion, sex, sexual orientation, marital status, pregnancy, parental status, national origin, ethnic background, age, disability, political opinion, social status, veteran status, union membership or genetics.

Ericsson complies with applicable country, state and all local laws governing nondiscrimination in employment in every location across the world in which the company has facilities. In addition, Ericsson supports the UN Guiding Principles for Business and Human Rights and the United Nations Global Compact.

This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, training and development.

Detta är en jobbannons med titeln "ASIC Synthesis & STA Engineer (231758)" hos företaget Ericsson AB och publicerades på webbjobb.io den 16 april 2018 klockan 00:00.

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